@inproceedings{d2087bdebcfa43dba5117f604e48e99e,
title = "SAT-based verification methods and applications in hardware",
abstract = "Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to HDD-based symbolic model checking methods. This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs. We focus separately on methods for finding bugs and for finding proofs for correctness properties, along with highlighting the many common themes that benefit these methods. We also describe practical experiences with these methods implemented in our verification platform called VeriSol (formerly DiVer), which has been used successfully in industry practice.",
author = "Aarti Gupta and Ganai, {Malay K.} and Chao Wang",
year = "2006",
doi = "10.1007/11757283_5",
language = "English (US)",
isbn = "3540343040",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "108--143",
booktitle = "Formal Methods for Hardware Verification - 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006",
address = "Germany",
note = "6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006 ; Conference date: 22-05-2006 Through 27-05-2006",
}