TY - GEN
T1 - SAT-based techniques for determining backbones for post-silicon fault localisation
AU - Zhu, Charlie Shucheng
AU - Weissenbacher, Georg
AU - Sethi, Divjyot
AU - Malik, Sharad
PY - 2011
Y1 - 2011
N2 - The localisation of faults in integrated circuits is a dominating factor in the overall verification effort. The limited observability of internal signals of chips complicates the spatial and temporal localisation of bugs in post-silicon validation. We address the problem of recovering the values of unobservable signals of a chip prototype from state bits recorded in a trace-buffer of limited size using a SAT-based analysis. Our technique is a novel application of backbones. This term refers to the set of parameters of a Boolean function that need to be fixed to a constant value for that function to evaluate to true. There is a range of known SAT-based techniques targeting this problem. We discuss a number of existing techniques and gradually extend these techniques with novel ideas, leading to novel and previously unstudied algorithms. We evaluate the performance of these algorithms using the aforementioned application in post-silicon validation. Our results show that these SAT-based techniques are suitable for large-scale applications with even millions of variables. Moreover, we evaluate the utility of backbones by quantifying the restored state bits in a number of case studies, including two processor cores.
AB - The localisation of faults in integrated circuits is a dominating factor in the overall verification effort. The limited observability of internal signals of chips complicates the spatial and temporal localisation of bugs in post-silicon validation. We address the problem of recovering the values of unobservable signals of a chip prototype from state bits recorded in a trace-buffer of limited size using a SAT-based analysis. Our technique is a novel application of backbones. This term refers to the set of parameters of a Boolean function that need to be fixed to a constant value for that function to evaluate to true. There is a range of known SAT-based techniques targeting this problem. We discuss a number of existing techniques and gradually extend these techniques with novel ideas, leading to novel and previously unstudied algorithms. We evaluate the performance of these algorithms using the aforementioned application in post-silicon validation. Our results show that these SAT-based techniques are suitable for large-scale applications with even millions of variables. Moreover, we evaluate the utility of backbones by quantifying the restored state bits in a number of case studies, including two processor cores.
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U2 - 10.1109/HLDVT.2011.6113981
DO - 10.1109/HLDVT.2011.6113981
M3 - Conference contribution
AN - SCOPUS:84856137908
SN - 9781457717444
T3 - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
SP - 84
EP - 91
BT - 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT'11
T2 - 16th IEEE International High Level Design Validation and Test Workshop, HLDVT'11
Y2 - 10 November 2011 through 11 November 2011
ER -