Runtime verification: A computer architecture perspective

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A major challenge in hardware verification is managing the state explosion problem in pre-silicon verification. This is seen in the high cost and low coverage of simulation, and capacity limitations of formal verification. Runtime verification, through on-the-fly property checking of the current trace and a low-cost error recovery mechanism, provides us an alternative attack in dealing with this problem. There are several interesting examples of runtime verification that have been proposed in recent years in the computer architecture community. These have also been motivated by the resiliency needs of future technology generations in the face of dynamic errors due to device failures. I will first highlight the key ideas in hardware runtime verification through specific examples from the uni-processor and multi-processor contexts. Next, I will discuss the challenges in implementing some of these solutions. Finally I will discuss how the strengths of runtime verification and model checking can be used in a complementary fashion for hardware.

Original languageEnglish (US)
Title of host publicationRuntime Verification - Second International Conference, RV 2011, Revised Selected Papers
Number of pages14
StatePublished - 2012
Event2nd International Conference on Runtime Verification, RV 2011 - San Francisco, CA, United States
Duration: Sep 27 2011Sep 30 2011

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume7186 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other2nd International Conference on Runtime Verification, RV 2011
Country/TerritoryUnited States
CitySan Francisco, CA

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • General Computer Science


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