In this paper a robustly testable design of static CMOS parity trees is presented. A test set for such a tree can be derived which cannot get invalidated in the presence of arbitrary input timing skews and/or circuit delays. The constituents of the parity tree are static CMOS xor gates, which are constructed from their corresponding binary decision diagrams (HDD’s). The xor gates in the tree can have any number of inputs. The robust test set detects all the single stuck-open, stuck-on, and stuck-at faults when both logic and current monitoring are done. We show that such implementations of parity trees are logarithmically testable, i.e., the size of the test set is proportional to the logarithm of the number of primary inputs.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering