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Robust testing of CMOS logic circuits
Niraj K. Jha
Electrical and Computer Engineering
Princeton Language and Intelligence (PLI)
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Keyphrases
CMOS Circuits
100%
Robustness Testing
100%
Stuck-at Faults
75%
Circuit Delay
50%
Two-pattern Tests
50%
Set-based
25%
Pattern Test
25%
Mathematics
Test Set
100%
Robust Test
50%