Robust testing of CMOS logic circuits

Research output: Contribution to journalArticle

Abstract

It is well-known that two-pattern tests, which are required to detect stuck-open faults in CMOS logic circuits, can be invalidated if circuit delays have been ignored in their derivation. Furthermore, for certain CMOS circuits a robust test set, which remains valid in the presence of arbitrary circuit delays, may not exist. However, for most CMOS circuits a robust test set does exist. In this paper we present a method for obtaining a test set based on two-pattern tests to robustly test for all single stuck-open faults. If the test set is based on three-pattern tests, then we show that it can detect all multiple stuck-open faults robustly.

Original languageEnglish (US)
Pages (from-to)19-28
Number of pages10
JournalComputers and Electrical Engineering
Volume15
Issue number1
DOIs
StatePublished - 1989

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Computer Science(all)
  • Electrical and Electronic Engineering

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