Ring systolic designs for artificial neural nets

This paper advocates digital VLSI architectures for implementing a wide variety of artificial neural nets (ANNs). A programmable systolic array is proposed which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant to be more general purpose than most other ANN architectures proposed. It may be used for a variety of algorithms in both the search and learning phases of ANNs. Although design considerations for the learning phase is somewhat more involved, our design can accommodate key learning rules, such as Hebbian, delta, competitive, and back-propagation learning rules. A numerical algebraic analysis permits much improved learning rates as compared with the existing techniques. Compared to analog neural circuits, the proposed systolic architecture offers higher flexibilities, higher precision, and full pipelinability.