@article{8d76f09aa222440994f16ee95c047447,
title = "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques",
abstract = "Sequential networks contain combinational logic blocks separated by registers. Application of combinational logic minimization techniques to the separate logic blocks results in improvement that is restricted by the placement of the registers; information about logical dependencies between blocks separated by registers is not utilized. Temporarily moving all the registers to the periphery of a network provides the combinational logic minimization tools with a global view of the logic. We propose a technique for optimizing a sequential network by moving the registers to the boundary of the network using an extension of retiming [8], [9], resynthesizing the combinational logic between the registers using existing logic minimization techniques, and replacing the registers throughout the network using retiming algorithms.",
author = "Sharad Malik and Sentovich, {Ellen M.} and Brayton, {Robert K.} and Alberto Sangiovanni-Vincentelli",
note = "Funding Information: 0VER THE past decade, combinational logic optimization h as attained a significant level of maturity. The problems and approaches in combinational logic synthesis are well understood: almost fully for the two-level logic case (e.g., [2]), and to a lesser extent in the multilevel logic case (e.g., [l], [3]). In comparison, sequential synthesis is just beginning to be recognized as a problem domain in its own right. Most existing efforts in sequential synthesis can be classified into three categories. The first approach is to consider the portions of combinational logic between register boundaries and use combinational logic optimization techniques on these separate blocks. However, this is restrictive inasmuch as it does not permit the interactions between gates separated by register boundaries to be examined in the optimization process. The second approach ([8], [9]) involves moving registers across portions of combinational logic in order to minimize the cycle time or the number of registers used. This procedure, termed retiming, does not change any of the combinational logic blocks. Thus it does not consider further optimizations that could have been obtained with that option. The third approach considers sequential circuits as implementations of finite state machine (FSM) descriptions. Operations on state transition graphs (STG{\textquoteright}s) and results from automata theory have been used to optimize implementations of STG{\textquoteright}s. One drawback with this approach is that all manipulations and optimizations are attempted at the STG level and it is not clear how these are reflected in the final gate-level implementations of the machine. Researchers have proposed different cost criteria such as the number of edges and the number of states in the STG as metrics for operations at the STG Manuscript received January I , 1990. This work was supported by the National Science Foundation under Grant EMC-8419744 and by DARPA under Grant N00039-C-87-0182. This paper was recommended by Guest Editor A. Sangiovanni-Vincentelli. The authors are with the Department of Electrical Engineering and Computer Science. University of California. Berkeley. CA 94720. IEEE Log Number 9039377.",
year = "1991",
month = jan,
doi = "10.1109/43.62793",
language = "English (US)",
volume = "10",
pages = "74--84",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",
}