This paper presents a novel approach for retargetable static software timing analysis. Specifically, we target the problem of determining bounds on the execution time of a program on modern processors, and solve this problem in a retargetable software development environment. Another contribution of this paper is the modeling of important features in contemporary architectures, such as branch prediction, predication, and instruction pre-fetching, which have great impact on system performance, and have been rarely handled thus far. These ideas allow to build a timing analysis tool that is efficient, accurate, modular and retargetable. We present preliminary results for sample embedded programs to demonstrate the applicability of the proposed approach.
|Number of pages
|Proceedings of the International Symposium on System Synthesis
|Published - 2001
|14th International Symposium on System Synthesis (ISSS'01) - Montreal, Que., Canada
Duration: Sep 30 2001 → Oct 3 2001
All Science Journal Classification (ASJC) codes
- Hardware and Architecture