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Resource budgeting for multiprocess high-level synthesis
Weidong Wang
, Anand Raghunathan
,
Niraj K. Jha
, Sujit Dey
Electrical and Computer Engineering
Princeton Language and Intelligence (PLI)
Research output
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Article
›
peer-review
4
Scopus citations
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Performance Process
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PRESENT Algorithm
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Design Flow
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Performance Analysis
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High-level Design
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Area Overhead
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Iterative Manner
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Register Transfer Level
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Area Consumption
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Trade-off Curve
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Process Scheduling
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Computer Science
Scheduling Process
60%
Interdependency
60%
Energy Delay Product
60%
Performance Analysis
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Register-Transfer-Level Implementation
60%