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Resource budgeting for multiprocess high-level synthesis
Weidong Wang
, Anand Raghunathan
,
Niraj K. Jha
, Sujit Dey
Electrical and Computer Engineering
Princeton Language and Intelligence (PLI)
Research output
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Contribution to journal
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Article
›
peer-review
4
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Scopus citations
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Keyphrases
High-level Synthesis
100%
Resource Budgeting
100%
Inter-process Communication
66%
Communicating Processes
66%
High-level Synthesis Tools
66%
Proposed Methodology
33%
Popular
33%
Power Delay Product
33%
Energy Consumption
33%
Performance Improvement
33%
Synthesis Methods
33%
Interprocess Synchronization
33%
Behavioral Description
33%
Communication Impact
33%
Digital System Design
33%
Hardware Description Language
33%
Digital Circuit Design
33%
Interdependency
33%
Performance Process
33%
Design Flow
33%
Performance Analysis
33%
High-level Design
33%
Area Overhead
33%
Iterative Manner
33%
Register Transfer Level
33%
Area Consumption
33%
Trade-off Curve
33%
Process Scheduling
33%
Performance Demands
33%
Process Specification
33%
Multi-process System
33%
Synthesis Steps
33%
Delay Tradeoff
33%
PRESENT Algorithm
33%
Computer Science
High Level Synthesis
100%
Synthesis Tool
40%
Interprocess Communication
40%
Communicating Process
40%
Energy Consumption
20%
Performance Improvement
20%
Digital Circuit
20%
Behavioral Description
20%
Process Specification
20%
Scheduling Process
20%
Interdependency
20%
Energy Delay Product
20%
Performance Analysis
20%
Register-Transfer-Level Implementation
20%
Synchronism
20%
Hardware Description Languages
20%