Abstract
This paper presents a register transfer modeling scheme for array processor simulation. Its main goals are to verify the application specific design by real data computation, and to help fine tune the array architecture by precise timing analysis. The data flow graph of the design is translated into a register transfer language which is further combined with a hardware description module. An interactive simulator SISim v2.0 has been implemented to simulate the behavior of such a system. The results are compared with the expected values to verify the array processor design. The recorded timing information can help the designer to analyze the system and improve the performance and resource utilization.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 111-122 |
| Number of pages | 12 |
| Journal | Proceedings of the International Conference on Application Specific Array Processors |
| State | Published - 1994 |
| Event | Proceedings of the 1994 International Conference on Application Specific Array Processors - San Francisco, CA, USA Duration: Aug 22 1994 → Aug 24 1994 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications