Register transfer level power optimization with emphasis on glitch analysis and reduction

Anand Raghunathan, Sujit Dey, Niraj K. Jha

Research output: Contribution to journalArticle

38 Scopus citations

Abstract

Design-for-low-power techniques for register-transfer level (RTL) controller/data path circuits are presented. The techniques include restructuring multiplexer networks, clocking control signals, and inserting selective rising/falling delays, in order to kill the propagation of glitches from control as well as data signals. In addition, a procedure is introduced to automatically perform the well-known power-reduction technique of clock gating through an efficient structural analysis of the RTL circuit, while avoiding the introduction of glitches on the clock. Application of the proposed power optimization techniques to RTL circuits shows significant power savings, with negligible area and delay overheads.

Original languageEnglish (US)
Pages (from-to)1114-1131
Number of pages18
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume18
Issue number8
DOIs
StatePublished - Jan 1 1999

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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