@inproceedings{66b3a13577ec4a1f9d98e436bdaeecab,

title = "Regenerative frequency divider with synchronous fractional outputs",

abstract = "This paper presents a regenerative frequency divider topology that provides two synchronous outputs of 1/N and (N -1)/N times the input frequency. This topology may lead to a saving in chip area and power consumption compared to cascaded divider chains trying to achieve the same division ratio. Design trade-offs are discussed following a theoretical treatment. A proof-of-concept divider with two synchronous outputs at 1/4 and 3/4 of the input frequency is designed in a 0.13 μm CMOS technology. The implemented divider achieves a locking range of 5% around 4 GHz for an input power of 8 dBm and a DC power consumption of 5 mW from a 1 V supply.",

keywords = "Divider circuits, Frequency synthesizers, Nonlinear circuits",

author = "Omeed Momeni and Kaushik Sengupta and Hossein Hashemi",

year = "2007",

month = oct,

day = "2",

doi = "10.1109/RFIC.2007.380983",

language = "English (US)",

isbn = "1424405319",

series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

pages = "717--720",

booktitle = "Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007",

note = "2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 ; Conference date: 03-06-2007 Through 05-06-2007",

}