Regenerative frequency divider with synchronous fractional outputs

Omeed Momeni, Kaushik Sengupta, Hossein Hashemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper presents a regenerative frequency divider topology that provides two synchronous outputs of 1/N and (N -1)/N times the input frequency. This topology may lead to a saving in chip area and power consumption compared to cascaded divider chains trying to achieve the same division ratio. Design trade-offs are discussed following a theoretical treatment. A proof-of-concept divider with two synchronous outputs at 1/4 and 3/4 of the input frequency is designed in a 0.13 μm CMOS technology. The implemented divider achieves a locking range of 5% around 4 GHz for an input power of 8 dBm and a DC power consumption of 5 mW from a 1 V supply.

Original languageEnglish (US)
Title of host publicationProceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
Pages717-720
Number of pages4
DOIs
StatePublished - Oct 2 2007
Externally publishedYes
Event2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 - Honolulu, HI, United States
Duration: Jun 3 2007Jun 5 2007

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Other

Other2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
CountryUnited States
CityHonolulu, HI
Period6/3/076/5/07

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Keywords

  • Divider circuits
  • Frequency synthesizers
  • Nonlinear circuits

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