Refining instruction set architecture for high-performance multimedia processing in constrained environments

Ruby Bei-Loh Lee, A. M. Fiskiran, Zhijie Shi, Xiao Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Multimedia processing in software has been significantly accelerated by the addition of subword-parallel instructions to the instruction set architectures (ISAs) of modem microprocessors. While some of these multimedia instructions are simple and effective, others are very complex, requiring large, special-purpose functional units that are not practical for constrained environments such as handheld multimedia information appliances. For such environments, low-power and low-cost are as important as the high performance required for real-time multimedia processing and the general-purpose programmability required to support an ever growing range of applications. In this paper, we introduce PLX, a concise ISA that selects the most useful features from the first two generations of multimedia instructions added to microprocessors, and explores new ISA features for high-performance yet low-cost multimedia processing with small footprint processors. PLX is unique in that it is designed from scratch as a fully subword-parallel architecture with novel features like datapath scalability from 32-bit to 128-bit words, and a new definition of predication for reducing conditional branches. We illustrate the use of PLX's architectural features with four frequently used multimedia kernels: discrete cosine transform, pixel padding, clip test and median filter. Our performance results show that a 64-bit PLX implementation achieves significant speedups compared to a basic 64-bit RISC processor and to IA-32 processors with MMX and SSE multimedia extensions. PLX's datapath scalability feature often provides an additional 2x speedup in a cost-effective way.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
EditorsRobert Schreiber, Shuvra Bhattacharyya, Neil Burgess, Michael Schulte
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages253-264
Number of pages12
ISBN (Electronic)0769517129
DOIs
StatePublished - Jan 1 2002
EventIEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 - San Jose, United States
Duration: Jul 17 2002Jul 19 2002

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume2002-January
ISSN (Print)1063-6862

Other

OtherIEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
CountryUnited States
CitySan Jose
Period7/17/027/19/02

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

Keywords

  • Acceleration
  • Computer architecture
  • Discrete cosine transforms
  • Home appliances
  • Instruction sets
  • Kernel
  • Microprocessors
  • Modems
  • Scalability
  • Testing

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