Redundancy identification and removal in combinational logic circuits

Tien Chien Lee, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In many logic circuit designs, redundancy is introduced unintentionally because of sub-optimal logic synthesis. Since such redundancy can cause larger area, longer delay, and worse testability, redundancy identification (RI) and removal (RR) have received constant attention in the area of logic synthesis. Previous works, mostly using automatic test pattern generation (ATPG) algorithms for RI, do not make full use of the functional specification from which the circuit is derived. This prevents one from identifying some redundancies whose removal does not violate the functional specification. Furthermore because removal of a redundancy may make other redundancies detectable, RI is usually performed again after each RR. But actually in a multi-output circuit, some of the remaining redundancies may be removable simultaneously with the first one if their removal is not invalidated by the first one. In this paper, we present an efficient RI and RR method for combinational logic circuits, called RIDAR, which can perform RI by taking advantage of the functional specification and can remove simultaneously more than one redundancy during one RR iteration. Experimental results show that significant savings in literal-count can be obtained for synthesized circuits in small amounts of CPU time. Surprisingly, we found that a significant reduction in literal-count can be obtained in many cases for combinational circuits even when conventional ATPG declares the circuit to be irredundant.

Original languageEnglish (US)
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1121-1124
Number of pages4
ISBN (Electronic)0780305930
DOIs
StatePublished - Jan 1 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: May 10 1992May 13 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period5/10/925/13/92

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Lee, T. C., & Jha, N. K. (1992). Redundancy identification and removal in combinational logic circuits. In 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 (pp. 1121-1124). [230282] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.1992.230282