Reducing test application time in high-level test generation

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations


Available register-transfer level (RTL) test generation techniques do not make a concerted effort to reduce the test application time associated with the derived tests. Chip tester memory limitations, increasing tester costs, etc., make it imperative that the issue of generating compact tests at the RTL be addressed and consolidated with the known gains of high-level testing. In this paper, we provide a comprehensive framework for generating compact tests for an RTL circuit. We develop a series of techniques that exploit the inherent parallelism available in symbolic test(s) derived for RTL module(s). These techniques enable us to schedule testing of multiple modules in parallel as well as perform test pipelining. In addition, we also present design for testability (DFT) techniques for lowering test application time. Using a maximum bipartite matching formulation, we choose a low-overhead set of test enhancements that can achieve compact tests. Our techniques can seamlessly plug into any generic high-level test framework. Our experimental results in the context of one such framework indicate that the proposed methodology achieves an average reduction in test application time of 61.1% for the example circuits.

Original languageEnglish (US)
Pages (from-to)829-838
Number of pages10
JournalIEEE International Test Conference (TC)
StatePublished - 2000

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics


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