Reducing quantization error in low-energy FIR filter accelerators

Zhuo Wang; Jintao Zhang; Naveen Verma

doi:10.1109/ICASSP.2015.7178126

Reducing quantization error in low-energy FIR filter accelerators

Zhuo Wang, Jintao Zhang, Naveen Verma

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

Computational energy versus computational precision represents a critical implementation-level tradeoff facing embedded DSP systems. Focusing on multiply-accumulate (MAC) hardware, which is used extensively in DSP implementations (e.g., FIR filtering), this paper proposes an approach that exploits floating-point representation of multipliers to enable optimization of their quantization error. The approach introduces a parameter α for coefficient scaling, and optimizes α to minimize the output error. Applied to FIR filters with coefficient representation of 6 bits, the approach reduces the quantization error by 37×, compared to traditional, linear-quantized fixed-point coefficient representation and by 28×, compared to unoptimized floating-point coefficient representation. Further, the energy and hardware gate-count of a MAC unit is reduced by 1.4× and 1.2×, respectively, compared to an implementation based on fixed-point representation.

Original language	English (US)
Title of host publication	2015 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1032-1036
Number of pages	5
ISBN (Electronic)	9781467369978
DOIs	https://doi.org/10.1109/ICASSP.2015.7178126
State	Published - Aug 4 2015
Event	40th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015 - Brisbane, Australia Duration: Apr 19 2014 → Apr 24 2014

Publication series

Name	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume	2015-August
ISSN (Print)	1520-6149

Other

Other	40th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015
Country/Territory	Australia
City	Brisbane
Period	4/19/14 → 4/24/14

All Science Journal Classification (ASJC) codes

Software
Signal Processing
Electrical and Electronic Engineering

Keywords

digital filter
embedded systems
floating point
low energy
quantization error

Access to Document

10.1109/ICASSP.2015.7178126

Cite this

Wang, Z., Zhang, J., & Verma, N. (2015). Reducing quantization error in low-energy FIR filter accelerators. In 2015 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015 - Proceedings (pp. 1032-1036). Article 7178126 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASSP.2015.7178126

Wang, Zhuo ; Zhang, Jintao ; Verma, Naveen. / Reducing quantization error in low-energy FIR filter accelerators. 2015 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1032-1036 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings).

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abstract = "Computational energy versus computational precision represents a critical implementation-level tradeoff facing embedded DSP systems. Focusing on multiply-accumulate (MAC) hardware, which is used extensively in DSP implementations (e.g., FIR filtering), this paper proposes an approach that exploits floating-point representation of multipliers to enable optimization of their quantization error. The approach introduces a parameter α for coefficient scaling, and optimizes α to minimize the output error. Applied to FIR filters with coefficient representation of 6 bits, the approach reduces the quantization error by 37×, compared to traditional, linear-quantized fixed-point coefficient representation and by 28×, compared to unoptimized floating-point coefficient representation. Further, the energy and hardware gate-count of a MAC unit is reduced by 1.4× and 1.2×, respectively, compared to an implementation based on fixed-point representation.",

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Wang, Z, Zhang, J & Verma, N 2015, Reducing quantization error in low-energy FIR filter accelerators. in 2015 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015 - Proceedings., 7178126, ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. 1032-1036, 40th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015, Brisbane, Australia, 4/19/14. https://doi.org/10.1109/ICASSP.2015.7178126

Reducing quantization error in low-energy FIR filter accelerators. / Wang, Zhuo; Zhang, Jintao; Verma, Naveen.
2015 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1032-1036 7178126 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Computational energy versus computational precision represents a critical implementation-level tradeoff facing embedded DSP systems. Focusing on multiply-accumulate (MAC) hardware, which is used extensively in DSP implementations (e.g., FIR filtering), this paper proposes an approach that exploits floating-point representation of multipliers to enable optimization of their quantization error. The approach introduces a parameter α for coefficient scaling, and optimizes α to minimize the output error. Applied to FIR filters with coefficient representation of 6 bits, the approach reduces the quantization error by 37×, compared to traditional, linear-quantized fixed-point coefficient representation and by 28×, compared to unoptimized floating-point coefficient representation. Further, the energy and hardware gate-count of a MAC unit is reduced by 1.4× and 1.2×, respectively, compared to an implementation based on fixed-point representation.

AB - Computational energy versus computational precision represents a critical implementation-level tradeoff facing embedded DSP systems. Focusing on multiply-accumulate (MAC) hardware, which is used extensively in DSP implementations (e.g., FIR filtering), this paper proposes an approach that exploits floating-point representation of multipliers to enable optimization of their quantization error. The approach introduces a parameter α for coefficient scaling, and optimizes α to minimize the output error. Applied to FIR filters with coefficient representation of 6 bits, the approach reduces the quantization error by 37×, compared to traditional, linear-quantized fixed-point coefficient representation and by 28×, compared to unoptimized floating-point coefficient representation. Further, the energy and hardware gate-count of a MAC unit is reduced by 1.4× and 1.2×, respectively, compared to an implementation based on fixed-point representation.

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Wang Z, Zhang J, Verma N. Reducing quantization error in low-energy FIR filter accelerators. In 2015 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1032-1036. 7178126. (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings). doi: 10.1109/ICASSP.2015.7178126

Reducing quantization error in low-energy FIR filter accelerators

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Keywords

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