S. Y. Kung, C. W. Chang, C. W. Jen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


In a real-time processing environment, reliability has become a major requirement for VLSI array processors. Three important fault-tolerance issues are discussed: how to minimize the testing, reconfiguration, and roll-back time; how to deal effectively with transient faults; and how to allocate spare processing elements (PEs). To improve the overall reliability performance, a reconfiguration algorithm which is distributively executed by all PEs is proposed. This reconfiguration algorithm can also be applied to a transient fault situation by deactivating and reactivating the temporary failed PE at appropriate times. A partition scheme for spare PE distribution is proposed which should significantly improve the system reliability. Finally, the timing analysis and the reliability performance for systolic and wavefront arrays are discussed.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
Number of pages9
ISBN (Print)0818607491
StatePublished - Dec 1 1986
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

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    Kung, S. Y., Chang, C. W., & Jen, C. W. (1986). REAL-TIME RECONFIGURATION FOR FAULT-TOLERANT VLSI ARRAY PROCESSORS. In Unknown Host Publication Title (pp. 46-54). IEEE.