In a real-time processing environment, reliability has become a major requirement for VLSI array processors. Three important fault-tolerance issues are discussed: how to minimize the testing, reconfiguration, and roll-back time; how to deal effectively with transient faults; and how to allocate spare processing elements (PEs). To improve the overall reliability performance, a reconfiguration algorithm which is distributively executed by all PEs is proposed. This reconfiguration algorithm can also be applied to a transient fault situation by deactivating and reactivating the temporary failed PE at appropriate times. A partition scheme for spare PE distribution is proposed which should significantly improve the system reliability. Finally, the timing analysis and the reliability performance for systolic and wavefront arrays are discussed.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Number of pages||9|
|State||Published - Dec 1 1986|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications