Random Fill Cache Architecture

Fangfei Liu, Ruby Bei-Loh Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

136 Scopus citations

Abstract

Correctly functioning caches have been shown to leak critical secrets like encryption keys, through various types of cache side-channel attacks. This nullifies the security provided by strong encryption and allows confidentiality breaches, impersonation attacks and fake services. Hence, future cache designs must consider security, ideally without degrading performance and power efficiency. We introduce a new classification of cache side channel attacks: contention based attacks and reuse based attacks. Previous secure cache designs target only contention based attacks, and we show that they cannot defend against reuse based attacks. We show the surprising insight that the fundamental demand fetch policy of a cache is a security vulnerability that causes the success of reuse based attacks. We propose a novel random fill cache architecture that replaces demand fetch with random cache fill within a configurable neighborhood window. We show that our random fill cache does not degrade performance, and in fact, improves the performance for some types of applications. We also show that it provides information-theoretic security against reuse based attacks.

Original languageEnglish (US)
Title of host publicationProceedings - 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014
PublisherIEEE Computer Society
Pages203-215
Number of pages13
EditionJanuary
ISBN (Electronic)9781479969982
DOIs
StatePublished - Jan 15 2015
Event47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014 - Cambridge, United Kingdom
Duration: Dec 13 2014Dec 17 2014

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
NumberJanuary
Volume2015-January
ISSN (Print)1072-4451

Other

Other47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014
Country/TerritoryUnited Kingdom
CityCambridge
Period12/13/1412/17/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • cache
  • cache collision attacks
  • computer architecture
  • secure caches
  • security
  • side channel attacks

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