Property-specific testbench generation for guided simulation

A. Gupta, A. E. Casavant, P. Ashar, X. G. Liu, A. Mukaiyama, K. Wakabayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Simulation continues to be the primary technique for functional validation of designs. It is important that simulation vectors be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The overall focus of our work is to generate a property-specific testbench for guided simulation, that is targeted either at proving the correctness of a property or at finding a bug. This is facilitated by generation of a properly-specific model, called a "witness graph", which captures interesting paths in the design. Starting from an initial abstract model of the design, symbolic model checking, pruning, and refinement steps are applied in an iterative manner, until either a conclusive result is obtained or computing resources are exhausted. This paper describes the theoretical underpinnings of generating and using a witness graph for computation tree logic (CTL) correctness properties, practical issues related to the generation of a testbench, and experiences with an industrial example. We have been able to demonstrate on a real in-house LSI design that such an approach can lead to significant reduction in the time required to analyze the design for a CTL property and find a witness.

Original languageEnglish (US)
Title of host publicationProceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages524-531
Number of pages8
ISBN (Electronic)0769514413, 9780769514413
DOIs
StatePublished - Jan 1 2002
Externally publishedYes
Event7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, India
Duration: Jan 7 2002Jan 11 2002

Publication series

NameProceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Other

Other7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
CountryIndia
CityBangalore
Period1/7/021/11/02

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Gupta, A., Casavant, A. E., Ashar, P., Liu, X. G., Mukaiyama, A., & Wakabayashi, K. (2002). Property-specific testbench generation for guided simulation. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 (pp. 524-531). [994973] (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2002.994973