Prediction of interconnect delay in logic synthesis

Henry H.F. Jyu, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

IC designers are now increasingly concerned about the delay due to interconnection wires. In the past, these effects have been largely ignored during logic design - primarily due to their negligible contributions and also because of the difficulty of predicting the wiring resulting from the subsequent layout stage. In this paper, an estimation model is proposed to predict the average wire length for each net in a given gate-level netlist and a particular layout tool.

Original languageEnglish (US)
Title of host publicationProceedings of the 1995 European Conference on Design and Test, EDTC 1995
PublisherAssociation for Computing Machinery, Inc
Pages411-415
Number of pages5
ISBN (Electronic)0818670398, 9780818670398
DOIs
StatePublished - Mar 6 1995
Event1995 European Conference on Design and Test, EDTC 1995 - Paris, France
Duration: Mar 6 1995Mar 9 1995

Publication series

NameProceedings of the 1995 European Conference on Design and Test, EDTC 1995

Other

Other1995 European Conference on Design and Test, EDTC 1995
CountryFrance
CityParis
Period3/6/953/9/95

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

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    Jyu, H. H. F., & Malik, S. (1995). Prediction of interconnect delay in logic synthesis. In Proceedings of the 1995 European Conference on Design and Test, EDTC 1995 (pp. 411-415). (Proceedings of the 1995 European Conference on Design and Test, EDTC 1995). Association for Computing Machinery, Inc. https://doi.org/10.1109/edtc.1995.470363