Prediction of interconnect delay in logic synthesis

Henry H.F. Jyu; Sharad Malik

doi:10.1109/edtc.1995.470363

Prediction of interconnect delay in logic synthesis

Henry H.F. Jyu, Sharad Malik

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

IC designers are now increasingly concerned about the delay due to interconnection wires. In the past, these effects have been largely ignored during logic design - primarily due to their negligible contributions and also because of the difficulty of predicting the wiring resulting from the subsequent layout stage. In this paper, an estimation model is proposed to predict the average wire length for each net in a given gate-level netlist and a particular layout tool.

Original language	English (US)
Title of host publication	Proceedings of the 1995 European Conference on Design and Test, EDTC 1995
Publisher	Association for Computing Machinery
Pages	411-415
Number of pages	5
ISBN (Electronic)	0818670398, 9780818670398
DOIs	https://doi.org/10.1109/edtc.1995.470363
State	Published - Mar 6 1995
Event	1995 European Conference on Design and Test, EDTC 1995 - Paris, France Duration: Mar 6 1995 → Mar 9 1995

Publication series

Name	Proceedings of the 1995 European Conference on Design and Test, EDTC 1995

Other

Other	1995 European Conference on Design and Test, EDTC 1995
Country/Territory	France
City	Paris
Period	3/6/95 → 3/9/95

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Industrial and Manufacturing Engineering

Access to Document

10.1109/edtc.1995.470363

Cite this

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title = "Prediction of interconnect delay in logic synthesis",

abstract = "IC designers are now increasingly concerned about the delay due to interconnection wires. In the past, these effects have been largely ignored during logic design - primarily due to their negligible contributions and also because of the difficulty of predicting the wiring resulting from the subsequent layout stage. In this paper, an estimation model is proposed to predict the average wire length for each net in a given gate-level netlist and a particular layout tool.",

author = "Jyu, {Henry H.F.} and Sharad Malik",

year = "1995",

month = mar,

day = "6",

doi = "10.1109/edtc.1995.470363",

language = "English (US)",

series = "Proceedings of the 1995 European Conference on Design and Test, EDTC 1995",

publisher = "Association for Computing Machinery",

pages = "411--415",

booktitle = "Proceedings of the 1995 European Conference on Design and Test, EDTC 1995",

note = "1995 European Conference on Design and Test, EDTC 1995 ; Conference date: 06-03-1995 Through 09-03-1995",

}

Jyu, HHF & Malik, S 1995, Prediction of interconnect delay in logic synthesis. in Proceedings of the 1995 European Conference on Design and Test, EDTC 1995. Proceedings of the 1995 European Conference on Design and Test, EDTC 1995, Association for Computing Machinery, pp. 411-415, 1995 European Conference on Design and Test, EDTC 1995, Paris, France, 3/6/95. https://doi.org/10.1109/edtc.1995.470363

Prediction of interconnect delay in logic synthesis. / Jyu, Henry H.F.; Malik, Sharad.
Proceedings of the 1995 European Conference on Design and Test, EDTC 1995. Association for Computing Machinery, 1995. p. 411-415 (Proceedings of the 1995 European Conference on Design and Test, EDTC 1995).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Prediction of interconnect delay in logic synthesis

AU - Jyu, Henry H.F.

AU - Malik, Sharad

PY - 1995/3/6

Y1 - 1995/3/6

N2 - IC designers are now increasingly concerned about the delay due to interconnection wires. In the past, these effects have been largely ignored during logic design - primarily due to their negligible contributions and also because of the difficulty of predicting the wiring resulting from the subsequent layout stage. In this paper, an estimation model is proposed to predict the average wire length for each net in a given gate-level netlist and a particular layout tool.

AB - IC designers are now increasingly concerned about the delay due to interconnection wires. In the past, these effects have been largely ignored during logic design - primarily due to their negligible contributions and also because of the difficulty of predicting the wiring resulting from the subsequent layout stage. In this paper, an estimation model is proposed to predict the average wire length for each net in a given gate-level netlist and a particular layout tool.

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M3 - Conference contribution

AN - SCOPUS:84893793784

T3 - Proceedings of the 1995 European Conference on Design and Test, EDTC 1995

SP - 411

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BT - Proceedings of the 1995 European Conference on Design and Test, EDTC 1995

PB - Association for Computing Machinery

T2 - 1995 European Conference on Design and Test, EDTC 1995

Y2 - 6 March 1995 through 9 March 1995

ER -

Prediction of interconnect delay in logic synthesis

Abstract

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All Science Journal Classification (ASJC) codes

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