Cycles arise in combinatorial logic circuits under a variety of different circumstances. Typically a cyclic combinatorial circuit consists of a set of acyclic circuits multiplexed to share resources in a cyclic topology. Recently Malik  provided an algorithm for deciding if a given circuit with cycles is combinational and also an algorithm for static timing analysis of such circuits. The logical analysis technique was based on OBDDs and the timing analysis technique was based on solving the false path problem for a large and complex circuit. As a result that method does not scale well to very large circuits. Prior to the present work, the only option left for designers was to do a case analysis by manually identifying the different acyclic circuits multiplexed in the cyclic structure, and then performing logical and timing analysis on this set of acyclic circuits. In this paper, we provide an analysis technique that automatically identifies the set of acyclic circuits constituting the cyclic circuit. This enables designers to directly use existing logical and timing analysis tools on this set of acyclic circuits. In addition to providing a more intuitive analysis, the proposed algorithm also scales easily to handle the very large circuits encountered in practice, with runtimes of a few hundred seconds on circuits with over 15000 gates.
|Number of pages
|Proceedings of the Custom Integrated Circuits Conference
|Published - 1996
|Proceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: May 5 1996 → May 8 1996
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering