Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems

Jiong Luo; N. K. Jha

doi:10.1109/ICVD.2003.1183164

Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems

Jiong Luo, N. K. Jha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

41 Scopus citations

Abstract

Presents a power-aware real-time distributed embedded system scheduling algorithm. It tries to satisfy the hard real-time constraints and precedence relationships of the tasks in the distributed embedded system specification. At the same time, it performs variable voltage scaling by addressing variations in power consumption of different tasks and characteristics of different voltage-scalable processing elements (PEs) in an effective and efficient manner. It performs execution order optimization of scheduled events to increase the chances of scaling down voltages and frequencies of these voltage-scalable PEs in the distributed embedded system. It also performs power-profile and timing-constraint driven slack allocation to maximize power reduction via voltage scaling. This scheduling algorithm is also very effective in the case where the variations in power consumption of different tasks can be ignored. It can be included in the inner loop of a system-level synthesis tool for real-time heterogeneous embedded systems since it is very fast. It is superior to other approaches in the literature in terms of power consumption or complexity.

Original language	English (US)
Title of host publication	Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
Publisher	IEEE Computer Society
Pages	369-375
Number of pages	7
ISBN (Electronic)	0769518680
DOIs	https://doi.org/10.1109/ICVD.2003.1183164
State	Published - 2003
Event	16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India Duration: Jan 4 2003 → Jan 8 2003

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
Volume	2003-January
ISSN (Print)	1063-9667

Other

Other	16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
Country/Territory	India
City	New Delhi
Period	1/4/03 → 1/8/03

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Keywords

Embedded system
Real time systems
Very large scale integration
Voltage

Access to Document

10.1109/ICVD.2003.1183164

Cite this

Luo, J., & Jha, N. K. (2003). Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems. In Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design (pp. 369-375). Article 1183164 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2003-January). IEEE Computer Society. https://doi.org/10.1109/ICVD.2003.1183164

Luo, Jiong ; Jha, N. K. / Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems. Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society, 2003. pp. 369-375 (Proceedings of the IEEE International Conference on VLSI Design).

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title = "Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems",

abstract = "Presents a power-aware real-time distributed embedded system scheduling algorithm. It tries to satisfy the hard real-time constraints and precedence relationships of the tasks in the distributed embedded system specification. At the same time, it performs variable voltage scaling by addressing variations in power consumption of different tasks and characteristics of different voltage-scalable processing elements (PEs) in an effective and efficient manner. It performs execution order optimization of scheduled events to increase the chances of scaling down voltages and frequencies of these voltage-scalable PEs in the distributed embedded system. It also performs power-profile and timing-constraint driven slack allocation to maximize power reduction via voltage scaling. This scheduling algorithm is also very effective in the case where the variations in power consumption of different tasks can be ignored. It can be included in the inner loop of a system-level synthesis tool for real-time heterogeneous embedded systems since it is very fast. It is superior to other approaches in the literature in terms of power consumption or complexity.",

keywords = "Embedded system, Real time systems, Very large scale integration, Voltage",

author = "Jiong Luo and Jha, {N. K.}",

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doi = "10.1109/ICVD.2003.1183164",

language = "English (US)",

series = "Proceedings of the IEEE International Conference on VLSI Design",

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Luo, J & Jha, NK 2003, Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems. in Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design., 1183164, Proceedings of the IEEE International Conference on VLSI Design, vol. 2003-January, IEEE Computer Society, pp. 369-375, 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design, New Delhi, India, 1/4/03. https://doi.org/10.1109/ICVD.2003.1183164

Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems. / Luo, Jiong; Jha, N. K.
Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society, 2003. p. 369-375 1183164 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Presents a power-aware real-time distributed embedded system scheduling algorithm. It tries to satisfy the hard real-time constraints and precedence relationships of the tasks in the distributed embedded system specification. At the same time, it performs variable voltage scaling by addressing variations in power consumption of different tasks and characteristics of different voltage-scalable processing elements (PEs) in an effective and efficient manner. It performs execution order optimization of scheduled events to increase the chances of scaling down voltages and frequencies of these voltage-scalable PEs in the distributed embedded system. It also performs power-profile and timing-constraint driven slack allocation to maximize power reduction via voltage scaling. This scheduling algorithm is also very effective in the case where the variations in power consumption of different tasks can be ignored. It can be included in the inner loop of a system-level synthesis tool for real-time heterogeneous embedded systems since it is very fast. It is superior to other approaches in the literature in terms of power consumption or complexity.

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Luo J, Jha NK. Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems. In Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society. 2003. p. 369-375. 1183164. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/ICVD.2003.1183164

Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems

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All Science Journal Classification (ASJC) codes

Keywords

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