Power management methodology for high-level synthesis

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey

Research output: Contribution to conferencePaperpeer-review

13 Scopus citations


In this paper, we present a power management technique targeted towards high-level synthesis of data-dominated behavioral descriptions. Our method is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, we present a procedure for constraining variable assignment, so that the functional units in the synthesized architecture do not execute any spurious operations. Unlike many previously proposed power management techniques, our method does not have an attendant performance penalty. Experimental results indicate savings of up to 52.5% in power consumption over already power-optimized architectures, at area overheads not exceeding 6.4%.

Original languageEnglish (US)
Number of pages6
StatePublished - 1998
EventProceedings of the 1998 11th International Conference on VLSI Design - Chennai, India
Duration: Jan 4 1998Jan 7 1998


OtherProceedings of the 1998 11th International Conference on VLSI Design
CityChennai, India

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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