TY - JOUR
T1 - Power management in high-level synthesis
AU - Lakshminarayana, Ganesh
AU - Raghunathan, Anand
AU - Jha, Niraj K.
AU - Dey, Sujit
N1 - Funding Information:
Manuscript received December 15, 1997; revised May 15, 1998. The work of G. Lakshminarayana and N. K. Jha was supported in part by Alternative System Concepts under an SBIR Contract from Air Force Rome Laboratories and in part by the National Science Foundation under Grant MIP-9319269.
PY - 1999
Y1 - 1999
N2 - In this paper,1 we present a power-management methodology targeted toward high-level synthesis of data-dominated behavioral descriptions. It is founded on the observation that variable assignment can significantly affect power-management opportunities in the synthesized architecture, i.e., variable assignment determines whether or not spurious operations get executed by functional units in the architecture. We introduce perfectly power managed architectures, whose functional units do not execute any spurious operations. We present a variable assignment technique which, when used in high-level synthesis, produces architectures which are perfectly power-managed. Unlike many previously proposed power-management techniques, our method does not add latches or any other circuitry in front of functional units or registers and is, therefore, free of the attendant performance penalty. Experimental results indicate savings of up to 52.5% (average 23.0%) in power consumption over already power-optimized architectures. The area overheads due to our technique are also low and averaged 2.5% for our examples.
AB - In this paper,1 we present a power-management methodology targeted toward high-level synthesis of data-dominated behavioral descriptions. It is founded on the observation that variable assignment can significantly affect power-management opportunities in the synthesized architecture, i.e., variable assignment determines whether or not spurious operations get executed by functional units in the architecture. We introduce perfectly power managed architectures, whose functional units do not execute any spurious operations. We present a variable assignment technique which, when used in high-level synthesis, produces architectures which are perfectly power-managed. Unlike many previously proposed power-management techniques, our method does not add latches or any other circuitry in front of functional units or registers and is, therefore, free of the attendant performance penalty. Experimental results indicate savings of up to 52.5% (average 23.0%) in power consumption over already power-optimized architectures. The area overheads due to our technique are also low and averaged 2.5% for our examples.
KW - Digital system design
KW - High-level synthesis
KW - Power management
KW - Register sharing
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U2 - 10.1109/92.748195
DO - 10.1109/92.748195
M3 - Article
AN - SCOPUS:0033097603
SN - 1063-8210
VL - 7
SP - 7
EP - 15
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 1
ER -