Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links

Li Shang; Li Shiuan Peh; Niraj K. Jha

doi:10.1109/L-CA.2002.10

Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links

Li Shang, Li Shiuan Peh, Niraj K. Jha

Electrical Engineering

Research output: Contribution to journal › Article

41 Scopus citations

Abstract

Power consumption is a key issue in high- performance interconnection network design. Communication links, already a significant consumer of power now, will take up an ever larger portion of the power budget as demand for network bandwidth increases. In this paper, we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS algorithm that judiciously adjusts DVS policies based on past link utilization. Despite very conservative assumptions about DVS link characteristics, our approach realizes up to 4.3X power savings (3.2X average), with just an average 27.4% latency increase and 2.5% throughput reduction. To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.

Original language	English (US)
Number of pages	1
Journal	IEEE Computer Architecture Letters
Volume	1
Issue number	1
DOIs	https://doi.org/10.1109/L-CA.2002.10
State	Published - Jan 1 2002

All Science Journal Classification (ASJC) codes

Hardware and Architecture

Access to Document

10.1109/L-CA.2002.10

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Shang, L., Peh, L. S., & Jha, N. K. (2002). Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links. IEEE Computer Architecture Letters, 1(1). https://doi.org/10.1109/L-CA.2002.10

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