Power-efficient computer architectures: Recent advances

Magnus Själander, Margaret Rose Martonosi, Stefanos Kaxiras

Research output: Chapter in Book/Report/Conference proceedingChapter

10 Scopus citations

Abstract

As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture.

Original languageEnglish (US)
Title of host publicationPower-Efficient Computer Architectures
Subtitle of host publicationRecent Advances
EditorsMargaret Martonosi, Mark D. Hill
PublisherMorgan and Claypool Publishers
Pages1-96
Number of pages96
ISBN (Electronic)9781627056458
DOIs
StatePublished - Dec 1 2014

Publication series

NameSynthesis Lectures on Computer Architecture
Volume30
ISSN (Print)1935-3235
ISSN (Electronic)1935-3243

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • architecture
  • heterogeneity
  • parallelism
  • power

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    Själander, M., Martonosi, M. R., & Kaxiras, S. (2014). Power-efficient computer architectures: Recent advances. In M. Martonosi, & M. D. Hill (Eds.), Power-Efficient Computer Architectures: Recent Advances (pp. 1-96). (Synthesis Lectures on Computer Architecture; Vol. 30). Morgan and Claypool Publishers. https://doi.org/10.2200/S00611ED1V01Y201411CAC030