Power-efficient computer architectures: Recent advances

Magnus Själander, Margaret Rose Martonosi, Stefanos Kaxiras

Research output: Chapter in Book/Report/Conference proceedingChapter

14 Scopus citations


As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture.

Original languageEnglish (US)
Title of host publicationPower-Efficient Computer Architectures
Subtitle of host publicationRecent Advances
EditorsMargaret Martonosi, Mark D. Hill
PublisherMorgan and Claypool Publishers
Number of pages96
ISBN (Electronic)9781627056458
StatePublished - Dec 1 2014

Publication series

NameSynthesis Lectures on Computer Architecture
ISSN (Print)1935-3235
ISSN (Electronic)1935-3243

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


  • architecture
  • heterogeneity
  • parallelism
  • power


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