Power-driven design of router microarchitectures in on-chip networks

Hangsheng Wang, Li Shiuan Peh, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

249 Scopus citations

Abstract

As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-chip communication. The tight delay requirements faced by on-chip networks have resulted in prior microarchitectures being largely performance-driven. While performance is a critical metric, on-chip networks are also extremely power-constrained. In this paper, we investigate on-chip network microarchitectures from a power-driven perspective. We first analyze the power dissipation of existing network microarchitectures, highlighting insights that prompt us to devise several power-efficient network microarchitectures: segmented crossbar, cut-through crossbar and write-through buffer. We also study and uncover the power saving potential of existing network architecture: express cube. These techniques are evaluated with synthetic as well as real chip multiprocessor traces, showing a reduction in network power of up to 44.9%, along with no degradation in network performance, and even improved latency-throughput in some cases.

Original languageEnglish (US)
Title of host publicationProceedings - 36th International Symposium on Microarchitecture, MICRO 2003
PublisherIEEE Computer Society
Pages105-116
Number of pages12
ISBN (Electronic)076952043X
DOIs
StatePublished - Jan 1 2003
Event36th International Symposium on Microarchitecture, MICRO 2003 - San Diego, United States
Duration: Dec 3 2003Dec 5 2003

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
Volume2003-January
ISSN (Print)1072-4451

Other

Other36th International Symposium on Microarchitecture, MICRO 2003
CountryUnited States
CitySan Diego
Period12/3/0312/5/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • Bandwidth
  • Fabrics
  • Intelligent networks
  • Microarchitecture
  • Network-on-a-chip
  • Power dissipation
  • Power system interconnection
  • System-on-a-chip
  • Telecommunication traffic
  • Traffic control

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