Abstract
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specification of these systems. At present, however, power analysis tools can only be applied at the lower levels of the design-the circuit or gate level. It is either impractical or impossible to use the lower level tools to estimate the power cost of the software component of the system. This paper describes the first systematic attempt to model this power cost. A power analysis technique is developed that has been applied to two commercial microprocessors-Intel 486DX2 and Fujitsu SPARClite 934. This technique can be employed to evaluate the power cost of embedded software. This can help in verifying if a design meets its specified power constraints. Further, it can also be used to search the design space in software power optimization. Examples with power reduction of up to 40%, obtained by rewriting code using the information provided by the instruction level power model, illustrate the potential of this idea.
| Original language | English (US) |
|---|---|
| Title of host publication | Low-Power CMOS Design |
| Publisher | Wiley-IEEE Press |
| Pages | 533-541 |
| Number of pages | 9 |
| ISBN (Electronic) | 9780470545058 |
| ISBN (Print) | 9780780334298 |
| DOIs | |
| State | Published - Jan 1 1998 |
All Science Journal Classification (ASJC) codes
- General Engineering
- General Computer Science
- General Energy