Abstract
An instruction-level power analysis model is developed for an embedded DSP processor that is based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general-purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the DSP processor has a special architectural feature that allows instruction to be packed into pairs. The energy reduction possible through the use of this feature is studied.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 215-229 |
| Number of pages | 15 |
| Journal | Fujitsu Scientific and Technical Journal |
| Volume | 31 |
| Issue number | 2 |
| State | Published - 1995 |
All Science Journal Classification (ASJC) codes
- Human-Computer Interaction
- Hardware and Architecture
- Electrical and Electronic Engineering