Power analysis and low-power scheduling techniques for embedded DSP software

Mike Tien Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita

Research output: Contribution to journalConference article

17 Scopus citations

Abstract

This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been developed using this technique. Significant points of difference have been observed between this model and the ones developed earlier for some general-purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the DSP processor has a special architectural feature that allows instructions to be packed into pairs. The energy reduction possible through the use of this feature is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A micro-architectural power model for the multiplier is developed and analyzed for further energy minimization. A scheduling algorithm incorporating these new techniques is proposed to reduce the energy consumed by DSP software. Energy reductions varying from 11% to 56% have been observed for several example programs. These energy savings are real and have been verified through physical measurement.

Original languageEnglish (US)
Pages (from-to)110-115
Number of pages6
JournalProceedings of the International Symposium on System Synthesis
DOIs
StatePublished - Jan 1 1995
Externally publishedYes
EventProceedings of the 8th International Symposium on System Synthesis - Cannes, Fr
Duration: Sep 13 1995Sep 15 1995

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Power analysis and low-power scheduling techniques for embedded DSP software'. Together they form a unique fingerprint.

  • Cite this