TY - GEN
T1 - Poster:Value-Aware Scheduler for Energy Reduction
AU - Ma, Haiyue
AU - Xu, Kaifeng
AU - Wentzlaff, David
N1 - Publisher Copyright:
©2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Optimizing energy consumption for computing workloads is a critical challenge, especially as we push the limits of high-performance systems within resource constraints. An underexplored approach to reducing energy costs is exploiting value locality: the tendency of instructions to process similar operand values during execution. Instruction operand values have abundant similarities within the reachable instruction window, a factor that existing architectures currently ignore. This paper introduces the broad concept of instruction-level, value-aware scheduling, an approach that leverages value locality in the hardware scheduler. By redirecting instructions of similar operand values to move together down the pipeline, the scheduler can reduce switching activity and dynamic energy usage. Such value-aware design philosophy, capable of adapting to a diverse range of workloads and architectures, has potential to be applied in broader architectural improvements.
AB - Optimizing energy consumption for computing workloads is a critical challenge, especially as we push the limits of high-performance systems within resource constraints. An underexplored approach to reducing energy costs is exploiting value locality: the tendency of instructions to process similar operand values during execution. Instruction operand values have abundant similarities within the reachable instruction window, a factor that existing architectures currently ignore. This paper introduces the broad concept of instruction-level, value-aware scheduling, an approach that leverages value locality in the hardware scheduler. By redirecting instructions of similar operand values to move together down the pipeline, the scheduler can reduce switching activity and dynamic energy usage. Such value-aware design philosophy, capable of adapting to a diverse range of workloads and architectures, has potential to be applied in broader architectural improvements.
UR - https://www.scopus.com/pages/publications/105031904109
UR - https://www.scopus.com/pages/publications/105031904109#tab=citedBy
U2 - 10.1109/PACT65351.2025.00051
DO - 10.1109/PACT65351.2025.00051
M3 - Conference contribution
AN - SCOPUS:105031904109
T3 - Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
SP - 470
EP - 472
BT - Proceedings - 2025 34th International Conference on Parallel Architectures and Compilation Techniques, PACT 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th International Conference on Parallel Architectures and Compilation Techniques, PACT 2025
Y2 - 3 November 2025 through 6 November 2025
ER -