Abstract
Several years of optimization on the cache-based super-scalar architecture has made it more difficult to port the current version of the 3D particle-in-cell code GTC to the NEC SX-6 vector architecture. This paper explains the initial work that has been done to port this code to the SX-6 computer and to optimize the most time consuming parts. After a few modifications, single-processor results show a performance increase of 5.2 compared to the IBM SP Power3 processor, and 2.7 compared to the Power4.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 456-458 |
| Number of pages | 3 |
| Journal | Computer Physics Communications |
| Volume | 164 |
| Issue number | 1-3 |
| DOIs | |
| State | Published - Dec 1 2004 |
| Event | Proceedings of the 18th International Conference - Falmouth, United States Duration: Sep 7 2003 → Sep 10 2003 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- General Physics and Astronomy
Keywords
- Code optimization
- Particle-in-cell
- Vector processor