PLX: An instruction set architecture and testbed for multimedia information processing

Ruby Bei-Loh Lee, A. Fiskiran

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance low-cost multimedia information processing. Unlike previous multimedia instruction sets PLX is not added onto a base processor ISA but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing general-purpose programmability to support an ever-growing range of applications simplicity for constrained environments where low power and low cost are paramount and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture microarchitecture arithmetic VLSI implementations compiler optimizations and parallel algorithm design for new computing paradigms. Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words a new definition of predication and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image video and graphics processing applications: discrete cosine transform pixel padding clip test and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLX's wordsize scalability feature PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through inter-instruction rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.

Original languageEnglish (US)
Pages (from-to)85-108
Number of pages24
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume40
Issue number1
DOIs
StatePublished - May 1 2005

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Information Systems
  • Electrical and Electronic Engineering

Keywords

  • ISA
  • Instruction set architecture
  • Media processing
  • Multimedia
  • Processor architecture

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