PLX: A fully subword-parallel instruction set architecture for fast scalable multimedia processing

Ruby B. Lee, A. Murat Fiskiran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Scopus citations

Abstract

PLX is a small, fully subword-parallel instruction set architecture (ISA) designed for very fast multimedia processing, especially in constrained environments requiring low cost and power, such as handheld multimedia information appliances. In PLX, we select the most useful multimedia instructions added previously to microprocessors. We also introduce a few novel features: a new definition of predication requiring very few bits in each predicated instruction, and datapath scalability from 32-bit to 128-bit words, which allows different degrees of subword parallelism without any changes to the ISA. Performance results from basic multimedia kernels testify to PLX's superiority for multimedia processing.

Original languageEnglish (US)
Title of host publicationProceedings - 2002 IEEE International Conference on Multimedia and Expo, ICME 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages117-120
Number of pages4
ISBN (Electronic)0780373049
DOIs
StatePublished - 2002
Event2002 IEEE International Conference on Multimedia and Expo, ICME 2002 - Lausanne, Switzerland
Duration: Aug 26 2002Aug 29 2002

Publication series

NameProceedings - 2002 IEEE International Conference on Multimedia and Expo, ICME 2002
Volume2

Other

Other2002 IEEE International Conference on Multimedia and Expo, ICME 2002
Country/TerritorySwitzerland
CityLausanne
Period8/26/028/29/02

All Science Journal Classification (ASJC) codes

  • Archaeology
  • Electrical and Electronic Engineering

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