PiCL: A software-Transparent, persistent cache log for nonvolatile main memory

Tri Nguyen, David Wentzlaff

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Software-Transparent crash consistency is a promising direction to immediately reap the benefits of nonvolatile main memory (NVMM) without encumbering programmers with error-prone transactional semantics. Unfortunately, proposed hardware write-Ahead logging (WAL) schemes have high performance overhead, particularly for multi-core systems with many threads and big on-chip caches and NVMs with low random-Access performance. This paper proposes PiCL, a new WAL checkpointing mechanism that provides a low overhead, software-Transparent crash consistency solution for NVMM. PiCL introduces multi-undo logging, cache-driven logging, and asynchronous cache-scan to reduce random accesses and enable good row locality at the NVM. The key idea is that: by relaxing the durability timing of checkpoints, crash consistency can be provided with less than 1% performance overhead where 1.5x to 5.0x slowdown was typical with prior work. To demonstrate the feasibility of software-Transparent crash consistency, we fully implemented PiCL as an FPGA prototype in Verilog using the OpenPiton framework.

Original languageEnglish (US)
Title of host publicationProceedings - 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018
PublisherIEEE Computer Society
Pages507-519
Number of pages13
ISBN (Electronic)9781538662403
DOIs
StatePublished - Dec 12 2018
Event51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018 - Fukuoka, Japan
Duration: Oct 20 2018Oct 24 2018

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
Volume2018-October
ISSN (Print)1072-4451

Other

Other51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018
CountryJapan
CityFukuoka
Period10/20/1810/24/18

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • Cache memory
  • Checkpointing
  • Computer crashes
  • Nonvolatile memory
  • Parallel processing

Fingerprint Dive into the research topics of 'PiCL: A software-Transparent, persistent cache log for nonvolatile main memory'. Together they form a unique fingerprint.

  • Cite this

    Nguyen, T., & Wentzlaff, D. (2018). PiCL: A software-Transparent, persistent cache log for nonvolatile main memory. In Proceedings - 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018 (pp. 507-519). [8574565] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO; Vol. 2018-October). IEEE Computer Society. https://doi.org/10.1109/MICRO.2018.00048