@inproceedings{0899144fa07d458db9dcc5b4bb49e5d2,
title = "PiCL: A software-Transparent, persistent cache log for nonvolatile main memory",
abstract = "Software-Transparent crash consistency is a promising direction to immediately reap the benefits of nonvolatile main memory (NVMM) without encumbering programmers with error-prone transactional semantics. Unfortunately, proposed hardware write-Ahead logging (WAL) schemes have high performance overhead, particularly for multi-core systems with many threads and big on-chip caches and NVMs with low random-Access performance. This paper proposes PiCL, a new WAL checkpointing mechanism that provides a low overhead, software-Transparent crash consistency solution for NVMM. PiCL introduces multi-undo logging, cache-driven logging, and asynchronous cache-scan to reduce random accesses and enable good row locality at the NVM. The key idea is that: by relaxing the durability timing of checkpoints, crash consistency can be provided with less than 1% performance overhead where 1.5x to 5.0x slowdown was typical with prior work. To demonstrate the feasibility of software-Transparent crash consistency, we fully implemented PiCL as an FPGA prototype in Verilog using the OpenPiton framework.",
keywords = "Cache memory, Checkpointing, Computer crashes, Nonvolatile memory, Parallel processing",
author = "Tri Nguyen and David Wentzlaff",
note = "Funding Information: This material is based on research sponsored by the NSF under Grants No. CNS-1823222 and CCF-1438980, AFOSR under Grant No. FA9550-14-1-0148, Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement No. FA8650-18-2-7846 and FA8650-18-2-7852.The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA), the NSF, AFOSR, DARPA, or the U.S. Government. Publisher Copyright: {\textcopyright} 2018 IEEE.; 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018 ; Conference date: 20-10-2018 Through 24-10-2018",
year = "2018",
month = dec,
day = "12",
doi = "10.1109/MICRO.2018.00048",
language = "English (US)",
series = "Proceedings of the Annual International Symposium on Microarchitecture, MICRO",
publisher = "IEEE Computer Society",
pages = "507--519",
booktitle = "Proceedings - 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018",
address = "United States",
}