Phase characterization for power: Evaluating control-flow-based and event-counter-based techniques

Research output: Chapter in Book/Report/Conference proceedingConference contribution

65 Scopus citations

Abstract

Computer systems increasingly rely on dynamic, phase-based system management techniques, in which system hardware and software parameters may be altered or tuned at run-time for different program phases. Prior research has considered a range of possible phase analysis techniques, but has focused almost exclusively on performance-oriented phases; the notion of power-oriented phases has not been explored. Moreover, the bulk of phase-analysis studies have focused on simulation evaluation. There is need for real-system experiments that provide direct comparison of different practical techniques (such as control flow sampling, event counters, and power measurements) for gauging phase behavior. In this paper, we propose and evaluate a live, real-system measurement framework for collecting and analyzing power phases in running applications. Our experimental framework simultaneously collects control flow, performance counter and live power measurement information. Using this framework, we directly compare between code-oriented techniques (such as "basic block vectors") and performance counter techniques for characterizing power phases. Across a collection of both SPEC2000 benchmarks as well as mainstream desktop applications, our results indicate that both techniques are promising, but that performance counters consistently provide better representation of power behavior. For many of the experimented cases, basic block vectors demonstrate a strong relationship between the execution path and power consumption. However, there are instances where power behavior cannot be captured from control flow, for example due to differences in memory hierarchy performance. We demonstrate these with examples from real applications. Overall, counter-based techniques offer average classification errors of 1.9% for SPEC and 7.1% for other benchmarks, while basic block vectors achieve 2.9% average errors for SPEC and 11.7% for other benchmarks respectively.

Original languageEnglish (US)
Title of host publicationProceedings - Twelfth International Symposium on High-Performance Computer Architecture, 2006
Pages122-133
Number of pages12
DOIs
StatePublished - Sep 26 2006
EventTwelfth International Symposium on High-Performance Computer Architecture, 2006 - Austin, TX, United States
Duration: Feb 11 2006Feb 15 2006

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume2006
ISSN (Print)1530-0897

Other

OtherTwelfth International Symposium on High-Performance Computer Architecture, 2006
CountryUnited States
CityAustin, TX
Period2/11/062/15/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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