Permutation operations in block ciphers

R. B. Lee, R. L. Rivest, M. J.B. Robshaw, Z. J. Shi, Y. L. Yin

Research output: Chapter in Book/Report/Conference proceedingChapter


New and emerging applications can change the mix of operations commonly used within computer architectures. It is sometimes surprising when instruction-set architecture (ISA) innovations intended for one purpose are used for other (initially unintended) purposes. This chapter considers recent proposals for the processor support of families of bit-level permutations. From a processor architecture point of view, the ability to support very fast bit-level permutations may be viewed as a further validation of the basic word-orientation of processors, and their ability to support next-generation secure multimedia processing. However, bitwise permutations are also fundamental operations in many cryptographic primitives and we discuss the suitability of these new operations for cryptographic purposes.

Original languageEnglish (US)
Title of host publicationEmbedded Cryptographic Hardware
Subtitle of host publicationDesign and Security
PublisherNova Science Publishers, Inc.
Number of pages18
ISBN (Print)1594541450, 9781594541452
StatePublished - 2005

All Science Journal Classification (ASJC) codes

  • General Computer Science


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