This paper addresses the problem of checking the equivalence of two Boolean functions under arbitrary input permutations and/or input phase assignments. This problem has several applications in the synthesis and verification of combinational logic. It arises in the technology mapping stage of logic synthesis in finding a match from the cell library for parts of the technology independent circuit. In logic verification this is needed when the exact correspondence of inputs between the two circuits is not known. Exact solutions using exhaustive enumeration of the permutations and/or phase assignments are never a practical possibility, thus recourse is taken to heuristics that work well in practice. The approach presented in this paper computes a signature for each variable or phase of a variable that will help to establish correspondence of variables or phases of variables. The strength of the proposed approach depends on the ability to quickly derive a signature with minimum aliasing. Aliasing refers to two different variables or phases having the same signature, thus rendering this signature useless for the purpose of distinguishing between them. Experimental results on a large number of examples establish the efficacy of this approach.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- High level design tools
- synthesis and verification
- synthesis of field-programmable gate arrays