### Abstract

We consider the problem of minimizing the cycle time of a given pipelined circuit. Existing approaches are suboptimal since they do not consider the possibility of simultaneously resynthesizing the combinational logic and moving the latches using retiming. In [10] the idea of simultaneous retiming and resynthesis was introduced. We use the concepts presented there to optimize a pipelined circuit to meet a given cycle time. An instance of the pipelined cycle optimization problem is specified by the circuit, a set of input arrival times relative to the clock, a set of output required times relative to the clock, and a given cycle time that it must meet. Given the instance of the pipelined performance optimization problem we construct an instance of a combinational speedup problem. This is specified by a combinational logic circuit, a set of arrival times on the inputs, and a set of required times for the outputs which must be met. We then give a constructive proof that the pipelined problem has a solution if and only if the combinational problem has a solution. This result is significant since it shows it is enough to consider only the combinational speedup problem and all known techniques for that (e.g., [12], [13]) can be directly applied to generate a solution for the pipelined problem.

Original language | English (US) |
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Pages (from-to) | 568-578 |

Number of pages | 11 |

Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Volume | 12 |

Issue number | 5 |

DOIs | |

State | Published - May 1993 |

### All Science Journal Classification (ASJC) codes

- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering

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## Cite this

*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*,

*12*(5), 568-578. https://doi.org/10.1109/43.277605