Performance analysis and optimization of VLSI dataflow arrays

S. Y. Kung, P. S. Lewis, S. C. Lo

Research output: Contribution to journalArticle

15 Scopus citations

Abstract

Motivated primarily by their potential for VLSI implementation, wavefront arrays have recently attracted significant research interest. Relative to their systolic counterparts, the asynchronous, data-driven nature of wavefront arrays eliminates the need for global synchronization and control. However, performance analysis for wavefront arrays is more complex. In this paper we introduce a datallow graph model for the timing analysis of general (cyclic or acyclic), decision-free asynchronous architectures. We then show how the results of this analysis can be used to synthesize optimal (in terms of speed and storage) special-purpose hardware implementations of both general datallow arrays and regular wavefront arrays.

Original languageEnglish (US)
Pages (from-to)592-618
Number of pages27
JournalJournal of Parallel and Distributed Computing
Volume4
Issue number6
DOIs
StatePublished - Dec 1987
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

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