PAX: A datapath-scalable minimalist cryptographic processor for mobile devices

Ahmet Murat Fiskiran, Ruby B. Lee

Research output: Chapter in Book/Report/Conference proceedingChapter

4 Scopus citations

Abstract

PAX is a datapath-scalable, minimalist cryptographic processor architecture for mobile and wireless information appliances. PAX can fully utilize the high bandwidth connections offered by the existing and emerging wireless technologies, where the data transfer rates can reach 100 Mbps. PAX architecture is based on a simple RISC instruction set, which is extended with a few additional instructions that provide huge speedups in the cryptographic algorithms commonly used with security protocols on the Internet. For bulk encryption and hashing, a very low frequency 32-bit single-issue PAX processor is sufficient to match the 2.4 Mbps data rate of 3G cellular networks. To match the 54 Mbps data rate of the IEEE 802.11a/g WLAN connections, the clock rate needed is still significantly under that used in today's mobile information appliances such as Personal Digital Assistants (PDAs). The datapath scalability feature allows PAX to be implemented as a 32-bit, 64-bit, or 128-bit processor without any changes to the instruction set. Our results indicate that this feature provides four to six times additional speedup for bulk encryption and public-key cryptography.

Original languageEnglish (US)
Title of host publicationEmbedded Cryptographic Hardware
Subtitle of host publicationDesign and Security
PublisherNova Science Publishers, Inc.
Pages19-33
Number of pages15
ISBN (Print)1594541450, 9781594541452
StatePublished - Dec 1 2005

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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    Fiskiran, A. M., & Lee, R. B. (2005). PAX: A datapath-scalable minimalist cryptographic processor for mobile devices. In Embedded Cryptographic Hardware: Design and Security (pp. 19-33). Nova Science Publishers, Inc..