Pathlength reduction features in the PA-RISC architecture

Ruby Lee, Michael Mahon, Dale Morris

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

The authors describe representative pathlength reduction features of PA-RISC (reduced instruction set computer) instructions in memory accessing, functional operations, and instruction sequencing. To illustrate the multi-op instructions in PA-RISC, comparison is made with the MIPS instruction set, rather than with some hypothetical single-op RISC instructions. It is noted that, while other RISC architectures strive to enable short cycle times and single cycle instruction execution, PA-RISC also supports pathlength reduction, without impacting either the cycle time or the CPI. Frequent operations are combined into a single multi-op instruction. Subword data are also operated on in parallel, making full use of the datapath width. Such instruction level parallelism gives PA-RISC some of the advantages of a very simple VLIW (very long instruction word) architecture (with short 32-b instructions), in addition to the inherent advantages of a streamlined RISC architecture.

Original languageEnglish (US)
Title of host publicationDigest of Papers - IEEE Computer Society International Conference
PublisherPubl by IEEE
Pages129-135
Number of pages7
ISBN (Print)0818626550
StatePublished - Feb 1 1992
Event37th Annual IEEE International Computer Conference - COMPCON SPRING '92 - San Francisco, CA, USA
Duration: Feb 24 1992Feb 28 1992

Other

Other37th Annual IEEE International Computer Conference - COMPCON SPRING '92
CitySan Francisco, CA, USA
Period2/24/922/28/92

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Lee, R., Mahon, M., & Morris, D. (1992). Pathlength reduction features in the PA-RISC architecture. In Digest of Papers - IEEE Computer Society International Conference (pp. 129-135). Publ by IEEE.