Abstract
The authors describe representative pathlength reduction features of PA-RISC (reduced instruction set computer) instructions in memory accessing, functional operations, and instruction sequencing. To illustrate the multi-op instructions in PA-RISC, comparison is made with the MIPS instruction set, rather than with some hypothetical single-op RISC instructions. It is noted that, while other RISC architectures strive to enable short cycle times and single cycle instruction execution, PA-RISC also supports pathlength reduction, without impacting either the cycle time or the CPI. Frequent operations are combined into a single multi-op instruction. Subword data are also operated on in parallel, making full use of the datapath width. Such instruction level parallelism gives PA-RISC some of the advantages of a very simple VLIW (very long instruction word) architecture (with short 32-b instructions), in addition to the inherent advantages of a streamlined RISC architecture.
Original language | English (US) |
---|---|
Title of host publication | Digest of Papers - IEEE Computer Society International Conference |
Publisher | Publ by IEEE |
Pages | 129-135 |
Number of pages | 7 |
ISBN (Print) | 0818626550 |
State | Published - Feb 1 1992 |
Event | 37th Annual IEEE International Computer Conference - COMPCON SPRING '92 - San Francisco, CA, USA Duration: Feb 24 1992 → Feb 28 1992 |
Other
Other | 37th Annual IEEE International Computer Conference - COMPCON SPRING '92 |
---|---|
City | San Francisco, CA, USA |
Period | 2/24/92 → 2/28/92 |
All Science Journal Classification (ASJC) codes
- Engineering(all)