Abstract
A heuristic technique for producing near optimum partitioning of electronic components in circuit layouts is outlined.
Original language | English (US) |
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Pages (from-to) | 8-12 |
Number of pages | 5 |
Journal | Bell Laboratories Record |
Volume | 48 |
Issue number | 1 |
State | Published - 1970 |
All Science Journal Classification (ASJC) codes
- General Engineering