Parameterized memory/processor optimizing FORTRAN compiler for parallel computers

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new approach to generating low-conflict, parallel instructions for complex applications is introduced in this paper. This method is presented within the context of a FORTRAN compiler. An approximate simulator has been incorporated within a parallel-code / domain-decomposition loop within the compiler. The simulator estimates the performance of candidate instruction segments, and guides the selection of appropriate code transformations, heuristics, and data storage strategies. At present, many aspects of the target machine are parameterized, to permit investigations of a number of parallel-computer architectures. In this paper, the compiler is illustrated for a Navier-Stokes Computer target node application.

Original languageEnglish (US)
Title of host publicationProccedings of the Scalable High Performance Computing Conference-SHPCC-92
PublisherPubl by IEEE
Pages204-207
Number of pages4
ISBN (Print)0818627751
StatePublished - Dec 1 1992

Publication series

NameProccedings of the Scalable High Performance Computing Conference-SHPCC-92

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Nosenchuck, D. M. (1992). Parameterized memory/processor optimizing FORTRAN compiler for parallel computers. In Proccedings of the Scalable High Performance Computing Conference-SHPCC-92 (pp. 204-207). (Proccedings of the Scalable High Performance Computing Conference-SHPCC-92). Publ by IEEE.