TY - GEN
T1 - Parameterized memory/processor optimizing FORTRAN compiler for parallel computers
AU - Nosenchuck, Daniel M.
PY - 1992
Y1 - 1992
N2 - A new approach to generating low-conflict, parallel instructions for complex applications is introduced in this paper. This method is presented within the context of a FORTRAN compiler. An approximate simulator has been incorporated within a parallel-code / domain-decomposition loop within the compiler. The simulator estimates the performance of candidate instruction segments, and guides the selection of appropriate code transformations, heuristics, and data storage strategies. At present, many aspects of the target machine are parameterized, to permit investigations of a number of parallel-computer architectures. In this paper, the compiler is illustrated for a Navier-Stokes Computer target node application.
AB - A new approach to generating low-conflict, parallel instructions for complex applications is introduced in this paper. This method is presented within the context of a FORTRAN compiler. An approximate simulator has been incorporated within a parallel-code / domain-decomposition loop within the compiler. The simulator estimates the performance of candidate instruction segments, and guides the selection of appropriate code transformations, heuristics, and data storage strategies. At present, many aspects of the target machine are parameterized, to permit investigations of a number of parallel-computer architectures. In this paper, the compiler is illustrated for a Navier-Stokes Computer target node application.
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M3 - Conference contribution
AN - SCOPUS:0027001566
SN - 0818627751
T3 - Proccedings of the Scalable High Performance Computing Conference-SHPCC-92
SP - 204
EP - 207
BT - Proccedings of the Scalable High Performance Computing Conference-SHPCC-92
PB - Publ by IEEE
ER -