Parallel and pipelined VLSI implementation of a staged decoder for BCM signals

This paper is devoted to VLSI implementation of a staged decoder for Block-Coded Modulation (BCM). We first review a general parallel and pipelined implementation of the decoder and we identify the parameters to be considered for optimization. A particular BCM scheme, based on the 8-PSK signal set, is chosen for a case study. Several ideas are described leading to a code-optimized design, and hardware implementation is shown. Next, we evaluate the performance of our design. In particular it is shown that, by exploiting regularity, a simple structure which achieves a throughput rate of 10 Mbps can be implemented by using 23 K transistors and 2 Μ standard cells CMOS technology. Further optimization and simple stacking of ten processors on a single chip in a block-processing structure allows us to achieve a throughput rate of 100 Mbps with about 150 K transistors (38 K gates).