## Abstract

Quantum circuits consist of a cascade of quantum gates. In a physical design-unaware quantum logic circuit, a gate is assumed to operate on an arbitrary set of quantum bits (qubits), without considering the physical location of the qubits. However, in reality, physical qubits have to be placed on a grid. Each node of the grid represents a qubit. The grid implements the architecture of the quantum computer. A physical constraint often imposed is that quantum gates can only operate on adjacent qubits on the grid. Hence, a communication channel needs to be built if the qubits in the logical circuit are not adjacent. In this paper, we introduce a tool called the physical design-aware fault-tolerant quantum circuit synthesis (PAQCS). It contains two algorithms: one for physical qubit placement and another for routing of communications. With the help of these two algorithms, the overhead of converting a logical to a physical circuit is reduced by 30.1%, on an average, relative to previous work. The optimization algorithms in PAQCS are evaluated on circuits implemented using quantum operations supported by two different quantum physical machine descriptions and three quantum error-correcting codes. They reduce the number of primitive operations by 11.5%-68.6%, and the number of execution cycles by 16.9%-59.4%.

Original language | English (US) |
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Article number | 6867398 |

Pages (from-to) | 1221-1234 |

Number of pages | 14 |

Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |

Volume | 23 |

Issue number | 7 |

DOIs | |

State | Published - Jul 1 2015 |

## All Science Journal Classification (ASJC) codes

- Software
- Hardware and Architecture
- Electrical and Electronic Engineering

## Keywords

- Placement
- quantum computing
- quantum logic synthesis
- routing