Paged absolute addressing mode optimizations for embedded digital signal processors using post-pass data-flow analysis

Ashok Sudarsanam; Sharad Malik; Steve Tjiang; Stan Liao

doi:10.1023/A:1008810300304

Paged absolute addressing mode optimizations for embedded digital signal processors using post-pass data-flow analysis

Ashok Sudarsanam
, Sharad Malik
, Steve Tjiang
, Stan Liao

Research output: Contribution to journal › Article › peer-review

Abstract

A compiler support for an architectural feature, the paged absolute addressing mode, of two commercial digital signal processors (DSP), the TMS320C25 and TMS320C50 fixed-point DSPs, is presented. Some machine-dependent code optimizations are discussed to improve code density by exploiting this feature. Results demonstrate that for a set of typical DSP benchmarks, some of the optimizations reduce overall code size and data memory consumption by an average of 5% and 16%, respectively.

Original language	English (US)
Pages (from-to)	41-59
Number of pages	19
Journal	Design Automation for Embedded Systems
Volume	4
Issue number	1
DOIs	https://doi.org/10.1023/A:1008810300304
State	Published - 1999

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture

Access to Document

10.1023/A:1008810300304

Cite this

@article{d4bf7a6b7341446b9442a81e031b1c57,

title = "Paged absolute addressing mode optimizations for embedded digital signal processors using post-pass data-flow analysis",

abstract = "A compiler support for an architectural feature, the paged absolute addressing mode, of two commercial digital signal processors (DSP), the TMS320C25 and TMS320C50 fixed-point DSPs, is presented. Some machine-dependent code optimizations are discussed to improve code density by exploiting this feature. Results demonstrate that for a set of typical DSP benchmarks, some of the optimizations reduce overall code size and data memory consumption by an average of 5\% and 16\%, respectively.",

author = "Ashok Sudarsanam and Sharad Malik and Steve Tjiang and Stan Liao",

note = "Funding Information: This research was supported by NSF grant MIP9457396, DARPA grant DABT63-97-1-0002, and grants from Fujitsu Laboratories of America, Rockwell Semiconductor Systems, and the New Jersey Center for Multimedia Research.",

year = "1999",

doi = "10.1023/A:1008810300304",

language = "English (US)",

volume = "4",

pages = "41--59",

journal = "Design Automation for Embedded Systems",

issn = "0929-5585",

publisher = "Springer Netherlands",

number = "1",

}

TY - JOUR

T1 - Paged absolute addressing mode optimizations for embedded digital signal processors using post-pass data-flow analysis

AU - Sudarsanam, Ashok

AU - Malik, Sharad

AU - Tjiang, Steve

AU - Liao, Stan

N1 - Funding Information: This research was supported by NSF grant MIP9457396, DARPA grant DABT63-97-1-0002, and grants from Fujitsu Laboratories of America, Rockwell Semiconductor Systems, and the New Jersey Center for Multimedia Research.

PY - 1999

Y1 - 1999

N2 - A compiler support for an architectural feature, the paged absolute addressing mode, of two commercial digital signal processors (DSP), the TMS320C25 and TMS320C50 fixed-point DSPs, is presented. Some machine-dependent code optimizations are discussed to improve code density by exploiting this feature. Results demonstrate that for a set of typical DSP benchmarks, some of the optimizations reduce overall code size and data memory consumption by an average of 5% and 16%, respectively.

AB - A compiler support for an architectural feature, the paged absolute addressing mode, of two commercial digital signal processors (DSP), the TMS320C25 and TMS320C50 fixed-point DSPs, is presented. Some machine-dependent code optimizations are discussed to improve code density by exploiting this feature. Results demonstrate that for a set of typical DSP benchmarks, some of the optimizations reduce overall code size and data memory consumption by an average of 5% and 16%, respectively.

UR - https://www.scopus.com/pages/publications/0032682299

UR - https://www.scopus.com/pages/publications/0032682299#tab=citedBy

U2 - 10.1023/A:1008810300304

DO - 10.1023/A:1008810300304

M3 - Article

AN - SCOPUS:0032682299

SN - 0929-5585

VL - 4

SP - 41

EP - 59

JO - Design Automation for Embedded Systems

JF - Design Automation for Embedded Systems

IS - 1

ER -

Paged absolute addressing mode optimizations for embedded digital signal processors using post-pass data-flow analysis

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this