Paged absolute addressing mode optimizations for embedded digital signal processors using post-pass data-flow analysis

Ashok Sudarsanam, Sharad Malik, Steve Tjiang, Stan Liao

Research output: Contribution to journalArticle

Abstract

A compiler support for an architectural feature, the paged absolute addressing mode, of two commercial digital signal processors (DSP), the TMS320C25 and TMS320C50 fixed-point DSPs, is presented. Some machine-dependent code optimizations are discussed to improve code density by exploiting this feature. Results demonstrate that for a set of typical DSP benchmarks, some of the optimizations reduce overall code size and data memory consumption by an average of 5% and 16%, respectively.

Original languageEnglish (US)
Pages (from-to)41-59
Number of pages19
JournalDesign Automation for Embedded Systems
Volume4
Issue number1
DOIs
StatePublished - Jan 1 1999

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

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