A compiler support for an architectural feature, the paged absolute addressing mode, of two commercial digital signal processors (DSP), the TMS320C25 and TMS320C50 fixed-point DSPs, is presented. Some machine-dependent code optimizations are discussed to improve code density by exploiting this feature. Results demonstrate that for a set of typical DSP benchmarks, some of the optimizations reduce overall code size and data memory consumption by an average of 5% and 16%, respectively.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture