TY - JOUR
T1 - Paged absolute addressing mode optimizations for embedded digital signal processors using post-pass data-flow analysis
AU - Sudarsanam, Ashok
AU - Malik, Sharad
AU - Tjiang, Steve
AU - Liao, Stan
N1 - Funding Information:
This research was supported by NSF grant MIP9457396, DARPA grant DABT63-97-1-0002, and grants from Fujitsu Laboratories of America, Rockwell Semiconductor Systems, and the New Jersey Center for Multimedia Research.
PY - 1999
Y1 - 1999
N2 - A compiler support for an architectural feature, the paged absolute addressing mode, of two commercial digital signal processors (DSP), the TMS320C25 and TMS320C50 fixed-point DSPs, is presented. Some machine-dependent code optimizations are discussed to improve code density by exploiting this feature. Results demonstrate that for a set of typical DSP benchmarks, some of the optimizations reduce overall code size and data memory consumption by an average of 5% and 16%, respectively.
AB - A compiler support for an architectural feature, the paged absolute addressing mode, of two commercial digital signal processors (DSP), the TMS320C25 and TMS320C50 fixed-point DSPs, is presented. Some machine-dependent code optimizations are discussed to improve code density by exploiting this feature. Results demonstrate that for a set of typical DSP benchmarks, some of the optimizations reduce overall code size and data memory consumption by an average of 5% and 16%, respectively.
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U2 - 10.1023/A:1008810300304
DO - 10.1023/A:1008810300304
M3 - Article
AN - SCOPUS:0032682299
SN - 0929-5585
VL - 4
SP - 41
EP - 59
JO - Design Automation for Embedded Systems
JF - Design Automation for Embedded Systems
IS - 1
ER -