Optimum low-gate-field and high-gate-field stability of amorphous silicon thin-film transistors with a single plastic-compatible gate nitride deposition process

The threshold voltage stability of a-Si thin-film transistors (TFT's) is important both at low and high gate electric fields. Low gate voltage operation is required to drive OLEDs in pixels with low TFT power loss with the TFT in saturation. High gate voltages are needed for maximum gate switching speed [1], as desired for integrated display peripheral drivers. At low gate electric fields, the TFT threshold voltage shift is dominated by breaking of weak Si-Si bonds and electron trapping by the resulting dangling bonds, while at high gate field, electron trapping in the gate nitride dominates [2]. Therefore, different gate nitride processes are conventionally required for the best TFT stability at high and low gate voltages. In this abstract, (i) we demonstrate a single gate nitride deposition process (using standard PECVD growth) which is optimum for stability for both low-field driving and high-field switching applications. Furthermore, (ii) the nitride deposition temperature is limited to 300°C which is compatible with hightemperature clear plastic substrates[3], unlike the previous best low-field results which required 350°C [4].